library ieee;
use ieee.std_logic_1164.all;
use STD.textio.all;
use ieee.std_logic_textio.all;


Entity tb is
End Entity;

Architecture tb_arc of tb is

Component  cm is
  port (
		x,c,ck,reset: in std_logic;
		p: in std_logic_vector(7 downto 0); 
		y: out std_logic
		);
End Component;

signal tbck,tbreset,tbx,tby,tbc: std_logic:='0';
signal tbpasswd: std_logic_vector(7 downto 0) :=X"57";
file file_RESULTS : text;
signal message: std_logic_vector(95 downto 0) :=X"FFFFFFFFFFFFFFFFFFFFFFFF";

for all : cm use entity work.m(m_arc);

Begin
tbck<=not tbck after 5 us;
tbreset<='1' after 1 us,
		 '0' after 2 us;


m1: cm port map(tbx,tbc, tbck,tbreset,tbpasswd,tby);
tbx<=message(0);

message<='0'&message(95 downto 1) when tbck='1' and tbck'event;

p1: process
	variable nclock: integer:=0;
	variable v_OLINE     : line;
	Begin 
	
	
    file_open(file_RESULTS, "output_results.txt", write_mode);
	while nclock<103 loop
	
		if tbck='1' and tbck'event then
		   nclock:=nclock + 1;
		   if(nclock>7) then   
				write(v_OLINE,tby,right, 1);
				writeline(file_RESULTS,v_OLINE);
		   end if;
		end if;
	
		
	 wait on tbck;
		
	end loop;
    file_close(file_RESULTS);
	wait;
	
	End Process;
    

End Architecture;