library ieee; use ieee.std_logic_1164.all; Entity m is port ( x,c,ck,reset: in std_logic; p: in std_logic_vector(7 downto 0); y: out std_logic ); End Entity; Architecture m_arc of m is signal previous,out_shift,shifted,sh_in,cypher: std_logic_vector(7 downto 0):=X"00"; signal ripple: std_logic:='0'; signal counter : std_logic_vector(7 downto 0):=X"00"; Begin previous<=X"00" when reset='1'and reset'event else cypher when ripple='0' and ripple'event; sh_in<=x&sh_in(7 downto 1) when ck='1' and ck'event; with p(1 downto 0) select shifted<= sh_in when "00", sh_in(0)&sh_in(7 downto 1) when "01", sh_in(1 downto 0)&sh_in(7 downto 2) when "10", sh_in(2 downto 0)&sh_in(7 downto 3) when "11", shifted when others; cypher<=shifted xor p xor previous when ripple='1' and ripple'event; out_shift<= cypher when ripple='0' and ripple'event else out_shift(0)& out_shift(7 downto 1) when ck='1' and ck'event; y<=out_shift(0); proc: process(ck,reset,ripple) variable count: integer :=0; Begin if(reset='1' and reset'event) then count:=0; else if(ck='1' and ck'event) then count:=count+1; if(count=8) then count:=0; ripple<='1'; end if; else if(ripple='1' and ripple'event) then ripple<='0' after 1 us; End if; End if; End if; End process; End Architecture;