library ieee;
use ieee.std_logic_1164.all;


Entity tb is
End Entity;

Architecture tb_arc of tb is

signal tbreset, tbck,tbm,tbe: std_logic:='0';

signal tbx,tby : std_logic_vector(7 downto 0):=X"00";
signal tbc : std_logic_vector(2 downto 0):="000";

Component m is 
	port (X,Y: in std_logic_vector(7 downto 0);
	      clock,reset: in std_logic;
	      e,m: out std_logic;
	      c: out std_logic_vector(2 downto 0));
End Component;

for all: m use entity work.m(m_arc);

Begin
 tbck<= not tbck after 5 us;
 tbx<=X"01" after 15 us; 
 tbreset<='1' after 6 us,
          '0' after 7 us;
  
  mtest: m port map(tbx,tby,tbck,tbreset,tbe,tbm,tbc);       


End;