library ieee;
use ieee.std_logic_1164.all, ieee.numeric_std.all;

Entity macchina is

	port( mclock,mres: in std_logic; md: in std_logic_vector(7 downto 0);
		  z: out std_logic_vector(7 downto 0); e, mrout: out std_logic);

End entity;

Architecture macchina_arc of macchina is


Component c_cont8 is
port(	reset,ck: in std_logic;
		count: out std_logic_vector(7 downto 0);
		rip: out std_logic		
	);
End Component;

Component c_somm8 is
port(x1,x2:in std_logic_vector(7 downto 0);
	 rin:in std_logic;
	 rout: out std_logic;
	 z:out std_logic_vector(7 downto 0));
End Component;
for all: c_cont8 use entity work.cont8(cont8_arc);
for all: c_somm8 use entity work.somm8(somm8_arc);

signal mrip: std_logic;
signal somout,accumulator, conteggio,mcount: std_logic_vector(7 downto 0):=X"00";
Begin

cont_1: c_cont8 port map(mres, mclock, mcount,mrip);
conteggio<=md when mcount=X"00" and mclock='1' and mclock'event --mcount'event
		   else conteggio;
		   
accumulator<=X"00" when mres='1' and mres'event else
			 somout when mclock='1' and mclock'event and mcount>X"01" else
			 accumulator;

som_1: c_somm8 port map(md,accumulator,'0',mrout,somout);
e<='1';
z<=accumulator;

End Architecture;